#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
+#define AT91_PMC_DDR (1 << 2) /* DDR Clock */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
ddr2_conf(&ddr2);
/* enable DDR2 clock */
- writel(0x4, &pmc->scer);
+ writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
ddr2_conf(&ddr2);
/* enable DDR2 clock */
- writel(0x4, &pmc->scer);
+ writel(AT91_PMC_DDR, &pmc->scer);
/* Chip select 1 is for DDR2/SDRAM */
csa = readl(&matrix->ebicsa);
ddr2_conf(&ddr2);
/* enable DDR2 clock */
- writel(0x4, &pmc->scer);
+ writel(AT91_PMC_DDR, &pmc->scer);
/* Chip select 1 is for DDR2/SDRAM */
csa = readl(&matrix->ebicsa);
/* enable MPDDR clock */
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
- writel(0x4, &pmc->scer);
+ writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
/* enable MPDDR clock */
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
- writel(0x4, &pmc->scer);
+ writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
/* enable MPDDR clock */
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
- writel(0x4, &pmc->scer);
+ writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
/* enable MPDDR clock */
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
- writel(0x4, &pmc->scer);
+ writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
ddr2_conf(&ddr2);
/* enable DDR2 clock */
- writel(0x4, &pmc->scer);
+ writel(AT91_PMC_DDR, &pmc->scer);
/* DDRAM2 Controller initialize */
ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);